System-level verification of heterogeneous architecture based on System-on-Chip for radiation monitoring

 

Within the Radiation Protection (RP) Group at CERN, the Instrumentation & Logistics (IL) Section is responsible for the design and development of specialized equipment for radiation protection. Radiation monitoring is essential to enable CERN to operate its accelerator complex and related experiments while fulfilling its legal obligations to protect the public, the people working on CERN sites and the environment. In that stringent context, the RP-IL Section has developed a new generation of radiation monitors, the CROME System, whose critical functionalities have SIL 2 (Safety Integrity Level) requirements.

In the light of the development outlined above, we are seeking for a student looking for challenging topics and willing to work within a dynamic team in an exceptional environment. 

As a safety system, it is crucial to verify that the CROME system fully meets its functional safety requirements and that it does not behave inappropriately. The radiation monitoring system has an expected lifetime of more than ten years. During this period, requirements and needs may evolve. CROME exploits a heterogeneous system-on-chip composed of processors running an embedded Linux and an FPGA for real-time calculations and decision making. Both the software and the firmware that are running need to be regularly updated. Therefore, any new version must be re-verified.

To this end, we have defined a SIL 2 compliant functional verification methodology and have started the implementation of an automated verification software suite that allows for automated regression testing and which can be extended to future requirements.

We are looking for a student who will work on the following tasks:

• Contribute to the verification of the C software and VHDL firmware of a System-on-Chip: The student will research about state-of-the art of verification techniques and design and implement automated verification code. A potential method could be the co-simulation of C application software together with VHDL firmware in a virtual Linux environment on simulated target hardware.
• Contribute to the verification of VHDL code. The student will follow and enhance our functional verification methodology. He or she will extend the existing SystemVerilog UVM (Universal Verification Methodology) test bench with a particular focus on sub-system and system-level verification.

Being within one of the first teams at CERN that apply formal methods for verification, this position also provides lots of possibilities for research topics in this area. The student could contribute to the development of formal properties (SystemVerilog Assertions) that will be proven by existing formal verification tools (model checkers).

 

Needed skills

• Experience with programming languages, e.g. one of C/C++, MATLAB, Rust, Python
• Understanding of Linux systems, multi-threaded software (ideally the POSIX thread library), TCP/IP stack, network security
• Experience on FPGA development with focus on VHDL/Verilog simulation
• Understanding of object-orientated programming
• Knowledge of SystemVerilog or UVM (Universal Verification Methodology) would be an asset
• Knowledge of formal methods (theoretically or practically) would be a plus
• Experience with software development utilities (Git, Jira, Makefiles, …) would be a plus

 

Training Value

This project offers the opportunity to work within an experienced and international team of engineers and physicists. It comprises development and training activities in the area of software development and testing, functional verification of RTL code, co-simulation and electronics.

The project may be used as a Master’s thesis project, consisting of research and practical experience (depending on the university supervisor’s requirements) or as a practical experience only.